Index: elua-svn/SConstruct
===================================================================
--- elua-svn.orig/SConstruct	2011-03-12 19:00:47.788514711 +0100
+++ elua-svn/SConstruct	2011-03-12 21:12:28.548514709 +0100
@@ -238,6 +238,10 @@
 vars = Variables()
 
 vars.AddVariables(
+  MatchEnumVariable('bootloader',
+                    'Build for bootloader usage, default is none.',
+                    'none',
+                    allowed_values = [ 'none', 'emblod' ] ),
   MatchEnumVariable('target',
                     'build "regular" float lua or integer-only "lualong"', 
                     'lua',
Index: elua-svn/src/platform/avr32/MIZAR32/mizar32_conf.h
===================================================================
--- elua-svn.orig/src/platform/avr32/MIZAR32/mizar32_conf.h	2011-03-12 19:22:29.240514711 +0100
+++ elua-svn/src/platform/avr32/MIZAR32/mizar32_conf.h	2011-03-12 19:26:24.072514711 +0100
@@ -133,13 +133,19 @@
 // Use #define PIO_PINS_PER_PORT 0 if this isn't needed
 #define PIO_PIN_ARRAY         { 31, 32, 32, 14 }
 
+#ifdef BOOTLOADER_EMBLOD
+# define ELUA_FIRMWARE_SIZE 0x80000
+#else
+# define ELUA_FIRMWARE_SIZE 0
+#endif
+
 // Allocator data: define your free memory zones here in two arrays
 // (start address and end address)
 // On Mizar32, we just use the 32MB SDRAM without trying to use the 8K that is
 // free in the onboard 32KB RAM, thereby simplifying the memory management.
 //#define MEM_START_ADDRESS     { ( void* )end, ( void* )SDRAM }
 //#define MEM_END_ADDRESS       { ( void* )( 0x8000 - STACK_SIZE_TOTAL - 1 ), ( void* )( SDRAM + SDRAM_SIZE - 1 ) }
-#define MEM_START_ADDRESS     { ( void* )SDRAM }
+#define MEM_START_ADDRESS     { ( void* )( SDRAM + ELUA_FIRMWARE_SIZE ) }
 #define MEM_END_ADDRESS       { ( void* )( SDRAM + SDRAM_SIZE - 1 ) }
 
 // Interrupt list
Index: elua-svn/src/platform/avr32/at32uc3a0128_emblod.ld
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ elua-svn/src/platform/avr32/at32uc3a0128_emblod.ld	2011-03-12 21:09:53.592514711 +0100
@@ -0,0 +1,51 @@
+MEMORY
+{
+    sram (W!RX) : ORIGIN = 0x00000004, LENGTH = 0x00007FFC
+    sdram (WRX) : ORIGIN = 0xd0000000, LENGTH = 0x02000000
+    flash (RX) : ORIGIN = 0x80002000, LENGTH = 0x00020000 - 0x2000
+}
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        PROVIDE(stext = .);
+        KEEP(*(.start))
+        *(.text .text.*)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        *(.exception .exception.*)
+        . = ALIGN(4);
+        _etext = .;
+        PROVIDE(etext = .);
+    } >sdram
+
+    .data : AT (_etext)
+    {
+        . = ALIGN(4);
+        _data = .;
+        *(.ramfunc .ramfunc.* .fastrun .fastrun.*)
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        . = ALIGN(4);
+        _edata = .;
+    } >sram
+
+    .bss (NOLOAD) : {
+        _bss = .;
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+    } >sram
+
+    end = .;
+    _sstack = 0x00008000;
+}
Index: elua-svn/src/platform/avr32/conf.py
===================================================================
--- elua-svn.orig/src/platform/avr32/conf.py	2011-03-12 19:06:40.432514711 +0100
+++ elua-svn/src/platform/avr32/conf.py	2011-03-12 19:10:48.616514712 +0100
@@ -18,10 +18,17 @@
 
 # Prepend with path
 specific_files = " ".join( [ "src/platform/%s/%s" % ( platform, f ) for f in specific_files.split() ] )
-ldscript = "src/platform/%s/%s.ld" % ( platform, comp[ 'cpu' ].lower() )
+
+# Choose ldscript according to choice of bootloader
+if comp[ 'bootloader' ] == "none":
+    print "Compiling for FLASH execution"
+    ldscript = "src/platform/%s/%s.ld" % ( platform, comp[ 'cpu' ].lower() )
+else :
+    print "Compiling for SDRAM execution"
+    ldscript = "src/platform/%s/%s_%s.ld" % ( platform, comp[ 'cpu' ].lower(), comp[ 'bootloader'] )
 
 # Standard GCC Flags
-comp.Append(CCFLAGS = ['-ffunction-sections','-fdata-sections','-fno-strict-aliasing','-Wall'])
+comp.Append(CCFLAGS = ['-ffunction-sections','-fdata-sections','-fno-strict-aliasing','-Wall','-DBOOTLOADER_%s' %comp['bootloader'].upper()])
 comp.Append(LINKFLAGS = ['-nostartfiles','-nostdlib','-Wl,--gc-sections','-Wl,--allow-multiple-definition','-Wl,--relax','-Wl,--direct-data','-T',ldscript])
 comp.Append(ASFLAGS = ['-x','assembler-with-cpp','-c'])
 comp.Append(LIBS = ['c','gcc','m'])
Index: elua-svn/src/platform/avr32/platform.c
===================================================================
--- elua-svn.orig/src/platform/avr32/platform.c	2011-03-12 19:11:18.028514710 +0100
+++ elua-svn/src/platform/avr32/platform.c	2011-03-12 19:26:46.356514711 +0100
@@ -107,8 +107,12 @@
   pm_enable_clk32_no_wait( &AVR32_PM, AVR32_PM_OSCCTRL32_STARTUP_0_RCOSC );    
   
   // Initialize external memory if any.
+  // If we are using bootloader emBLOD, SDRAM is already set up
+  // and should not be reinitialized.
 #ifdef AVR32_SDRAMC
+# ifndef BOOTLOADER_EMBLOD
   sdramc_init( REQ_CPU_FREQ );
+# endif
 #endif 
       
   // Setup timers
Index: elua-svn/src/platform/avr32/pm_conf_clocks.c
===================================================================
--- elua-svn.orig/src/platform/avr32/pm_conf_clocks.c	2011-03-12 19:13:20.468514711 +0100
+++ elua-svn/src/platform/avr32/pm_conf_clocks.c	2011-03-12 20:05:53.896514711 +0100
@@ -82,8 +82,12 @@
   unsigned long pll_freq, rest;
   Bool b_div2_pba, b_div2_cpu;
 
-  // Switch to external Oscillator 0
+  // Switch to external Oscillator 0.
+  // If the bootloader emBLOD is used, we are already running PLL0 from OSC0
+  // and clocks should not be set again
+#ifndef BOOTLOADER_EMBLOD
   pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
+#endif
 
   // Start with CPU freq config
   if (in_cpu_f == in_osc0_f)
@@ -143,6 +147,9 @@
   param->cpu_f = pll_freq / (1 << div2_cpu);
   mul--;
 
+  // If the bootlaoder emBLOD is used, we are already running PLL0 from OSC0
+  // and clocks should not be set again
+#ifndef BOOTLOADER_EMBLOD
   pm_pll_setup(&AVR32_PM
   , 0   // pll
   , mul // mul
@@ -158,6 +165,7 @@
   , div2_en // pll_div2
   , 0 // pll_wbwdisable
   );
+#endif
 
   rest = pll_freq;
   while (rest > AVR32_PM_PBA_MAX_FREQ ||
@@ -172,11 +180,13 @@
   // Update real PBA Frequency
   param->pba_f = pll_freq / (1 << div2_pba);
 
+#ifndef BOOTLOADER_EMBLOD
   // Enable PLL0
   pm_pll_enable(&AVR32_PM, 0);
 
   // Wait for PLL0 locked
   pm_wait_for_pll0_locked(&AVR32_PM);
+#endif
 
   if (div2_cpu)
   {
@@ -194,11 +204,13 @@
   else
     b_div2_pba = FALSE;
 
+#ifndef BOOTLOADER_EMBLOD
   pm_cksel(&AVR32_PM
   , b_div2_pba, div2_pba // PBA
   , b_div2_cpu, div2_cpu // PBB
   , b_div2_cpu, div2_cpu // HSB
   );
+#endif
 
   if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)
   {
@@ -221,7 +233,9 @@
 #endif
   }
 
+#ifndef BOOTLOADER_EMBLOD
   pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
+#endif
 
   return PM_FREQ_STATUS_OK;
 }
