Possible bug in LPC17xx memory configuration?

classic Classic list List threaded Threaded
1 message Options
Amr Bekhit Amr Bekhit
Reply | Threaded
Open this post in threaded view

Possible bug in LPC17xx memory configuration?


I've been working on a new eLua platform for the LPC177x_8x series of chips based on the existing LPC17xx platform (which, despite the name similarity, actually have some fundamental differences to the LPC17xx series and so can't use the same platform). While looking through the LPC17xx memory configuration at the end of platform_conf.h, I think that the definition is incorrect. Here's what the LPC17xx definitions looks like:

#define MEM_END_ADDRESS       { ( void* )( SRAM_ORIGIN + SRAM_SIZE - STACK_SIZE_TOTAL - 1 ), ( void* )( SRAM2_ORIGIN + SRAM2_SIZE - 1 ) }

The definition for MEM_END_ADDRESS[0] implies that the stack is located right at very top of RAM (like in some of the other ARM ports, where the actual stack size is TOTAL_RAM - bss - data). However, for the LPC17xx port, the stack is declared as an array, pulStack, in the startup file and the linker places this array right after the data and bss sections, and so I think that the MEM_END_ADDRESS definition should be:

#define MEM_END_ADDRESS       { ( void* )( SRAM_ORIGIN + SRAM_SIZE - 1 ), ( void* )( SRAM2_ORIGIN + SRAM2_SIZE - 1 ) }

I modified conf.py so that the linker could generate a map file ( comp.Prepend(LINKFLAGS = [TARGET_FLAGS,'-Wl,-e,Reset_Handler','-Wl,-static','-Wl,-Map,' + comp[ 'cpu' ] + '.map']) ) and looking at the address that pulStack is located at confirms that it is not at the top of SRAM like in some of the other ports.

I suppose it's not really a "bug" in that I don't think it's going to cause any problems, but does give you an extra [STACK_SIZE] bytes of RAM for eLua!


eLua-dev mailing list
[hidden email]